The present invention relates to a semiconductor device and a circuit board, and particularly, relates to a technique effective when applied to a semiconductor device having a BGA (Ball Grid Array) structure.
In a plurality of semiconductor devices which are mounted on a circuit board such as a printed board, various discontinuities are present in a signal transmission path for transmitting a signal which is output from one semiconductor device to another semiconductor device, and thus the challenge is how to nullify the discontinuities. In recent years, particularly, in order to nullify impedance discontinuity, a technique for canceling impedance discontinuity using reverse impedance discontinuity has been widely adopted. In short, this technique is configured such that, for example, in case that capacitive (<50 ohm) impedance discontinuity is present in a signal transmission path, inductive (>50 ohm) impedance discontinuity is disposed next to a portion in which capacitive impedance discontinuity is present within the signal transmission path along a signal transmission direction, to reduce signal reflection by bringing average impedance close to 50 Ohm.
The related art of techniques for nullifying the above-mentioned impedance discontinuity is disclosed in JP-A-2004-253947; Nanju Na, Mark Bailey and Asad Kalantarian, “Package Performance Improvement with Counter-Discontinuity and its Effective Bandwidth”, Proceedings of 16th Topical meeting on Electrical Performance of Electronic Packaging, p. 163 to p. 168 (2007); and Namhoon Kim, Hongsik Ahn, Chris Wyland, Ray Anderson, Paul Wu, “Spiral Via Structure in a BGA Package to Mitigate Discontinuities in Multi-Gigabit SERDES System”, Proceedings of 60th Electronic Components and Technology Conference, p. 1474 to p. 1478 (2010).
JP-A-2004-253947 discloses a technique for serially connecting a third planar line having characteristic impedance higher than that of a first planar line to a fourth planar line having characteristic impedance higher than that of a second planar line, between the first planar line and the second planar line having characteristic impedance higher than that of the first planar line.
Nanju Na, Mark Bailey and Asad Kalantarian, “Package Performance Improvement with Counter-Discontinuity and its Effective Bandwidth”, Proceedings of 16th Topical meeting on Electrical Performance of Electronic Packaging, p. 163 to p. 168 (2007) discloses a technique for adjusting average impedance to 50 ohm by interposing the front and rear of a low impedance portion constituted by a through via and a solder ball pad in a high impedance line, as shown in FIG. 6 of the above document.
Namhoon Kim, Hongsik Ahn, Chris Wyland, Ray Anderson, Paul Wu, “Spiral Via Structure in a BGA Package to Mitigate Discontinuities in Multi-Gigabit SERDES System”, Proceedings of 60th Electronic Components and Technology Conference, p. 1474 to p. 1478 (2010) discloses a technique for adjusting average impedance of a signal transmission path including a low impedance portion constituted by a through via and a solder ball pad to 50 ohm, using a conductive layer having a shape of an inductor created by combining a small via and an interconnect pattern.